1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory and, in particular, to a structure of a NROM (nitride read only memory) type non-volatile semiconductor memory.
2. Description of the Background Art
FIG. 61 is a top view illustrating part of the structure of a conventional NROM type non-volatile semiconductor memory, and it schematically shows only the arrangement of word lines WL1 and WL2, bit lines BL1 and BL2, and channel regions CH1 to CH3. The word lines WL1 and WL2 extend in a predetermined direction (hereinafter referred to as xe2x80x9crow directionxe2x80x9d). The bit lines BL1 and BL2 extend in a direction orthogonal to the row direction (hereinafter referred to as xe2x80x9ccolumn direction). The channel regions CH1 to CH3 are disposed between bit lines adjacent with each other, and extend in the column direction.
FIG. 62 is a sectional view of a memory cell transistor structure, corresponding to a cross-sectional structure taken along the line A1xe2x80x94A1 in FIG. 61. LOCOS (local oxidation of silicon) type isolation insulating films 10612 and 10623 for defining an element-forming region are selectively formed in the upper surface of a silicon substrate 101. N+ type impurity diffusion regions 10712 and 10723 are formed at the interfacial portions between the silicon substrate 101 and the isolation insulating films 10612 and 10623. The impurity diffusion regions 10712 and 10723 correspond to the bit lines BL1 and BL2 shown in FIG. 61. The impurity diffusion regions 10712 and 10723 can be formed by introducing, by ion implantation method, an n-type impurity into the silicon substrate 101 beneath the isolation insulating films 10612 and 10623, and then subjecting the impurity to thermal diffusion.
ONO films 1051 to 1053 are formed on the upper surface of the silicon substrate 101 in the element-forming region. The ONO films 1051 to 1053 extend so as to overlie the end portions of the isolation insulating films 10612 and 10623. The ONO films 1051 to 1053 have such a three-layer structure that silicon oxide films 1021 to 1023, silicon nitride films 1031 to 1033, and silicon oxide films 1041 to 1043 are formed in this order on the silicon substrate 101. Unlike MNOS (metal nitride oxide semiconductor) type memory cell transistors, the silicon oxide films 1021 to 1023 and 1041 to 1043 have a thickness of not less than 5 nm, in order to prevent tunneling phenomenon of electrons.
A conductive film 1091 is disposed on the ONO films 1051 to 1053 and the isolation insulating films 10612 and 10623. The conductive film 1091 has, for example, polycide structure or polymetal structure. For the purpose of increasing the operation speed of memory cell transistors, it is preferable to employ polymetal structure having lower resistance than polycide structure. The conductive film 1091 corresponds to the word line WL1 shown in FIG. 61. P-type channel regions 1081 to 1083 are disposed in the upper surface of the silicon substrate 101 in the element-forming region. The channel regions 1081 to 1083 correspond to the channel regions CH1 to CH3 shown in FIG. 61. By adjusting the impurity concentration of the channel regions 1081 to 1083, the threshold voltage of the memory cell transistor can be set to a desired value.
The impurity diffusion regions 10712 and 10723 function as the source/drain regions of the memory cell transistors. The ONO films 1051 to 1053 function as the gate insulating film of the memory cell transistors. The conductive film 1091 overlying the ONO films 1051 to 1053 functions as the gate electrode of the memory cell transistors.
The isolation insulating films 10612 and 10623 are formed in the following manner. First, an ONO film is formed on the entire upper surface of a silicon substrate 101. The ONO film is then patterned to form ONO films 1051 to 1053, thereby to expose part of the upper surface of the silicon substrate 101. The exposed part of the silicon substrate 101 is then subjected to thermal oxidation, thereby forming isolation insulating films 10612 and 10623. Thus, by arranging such that the ONO films 1051 to 1053 function as an oxidation preventing mask in forming the isolation insulating films 10612 and 10623, in addition to the function of the gate insulating film of the memory cell transistor, the number of manufacturing steps can be reduced.
An NROM type non-volatile semiconductor memory, as will be described below, can store a 2-bit information in total, a 1-bit for each of two locations in one memory cell transistor. Referring to FIG. 61, the unit cell area of the NROM type non-volatile semiconductor memory is 2Fxc3x972.5F=5F2, wherein F (featured size) corresponds to a design rule. When F=0.35 xcexcm, 5F2=0.6125 xcexcm2. When F=0.25 xcexcm, 5F2=0.3125 xcexcm2. The NROM type non-volatile semiconductor memory can be manufactured relatively easily only by adding four photomasks (two of which are for memory cell, and the remainder for peripheral circuit) to existing CMOS process. For the reason for this, the NROM type non-volatile semiconductor memory has the features of having high storage density and low manufacturing cost.
The operation of a NROM type memory cell transistor will now be fully described. The NROM type memory cell transistor can store a 1-bit information at each of two locations of one memory cell transistor. In the present specification, one location storing information is defined as xe2x80x9cBit Rxe2x80x9d, and the other location is defined as xe2x80x9cBit Lxe2x80x9d.
FIGS. 63(A) and 63(B) are schematic diagrams illustrating write operation. FIG. 63(A) shows the write operation to the Bit R. A voltage of VS=0 V is applied to an impurity diffusion region 10712 functioning as a source region, a voltage of VD=4 V is applied to an impurity diffusion region 10723 functioning as a drain region, and a voltage of VG=8 V is applied to a gate electrode 1091. Thereby, channel hot electrons are introduced via a silicon oxide film 1022 into a silicon nitride film 1032, and the introduced electrons are then trapped and stored by traps (also called trap levels or trap centers) which are discretely distributed in the silicon nitride film 1032. Unlike electrons stored in a floating gate such as of a flash memory, the electrons stored in the silicon nitride film 1032 are less dispersible in a lateral direction (the gate length direction) in the silicon nitride film 1032. The number of electrons needed in writing is as few as 200 to 500, and writing is completed in a short time of about 100 ns. By reversing the voltages applied to the impurity diffusion regions 10712 and 10723, writing to the Bit L can be performed as shown in FIG. 63(B).
FIGS. 64(A) and 64(B) are schematic diagrams illustrating erase operation. FIG. 64(A) shows an erase operation related to the Bit R. A voltage of VSD12=0 V is applied to the impurity diffusion region 10712, a voltage of VSD23=4 V is applied to the impurity diffusion region 10723, and a voltage of VG=xe2x88x926 V is applied to the gate electrode 1091. Thereby, there occurs a potential difference between the silicon substrate 101 (or the channel region 1082) and the impurity diffusion region 10723. As a result, the energy bands of the silicon substrate 101 is curved, and interband tunnel current flows. By the interband tunnel current, hot holes are induced, and the hot holes are attracted by the gate voltage of xe2x88x926 V and then introduced into the silicon nitride film 1032 via the silicon oxide film 1022. The introduced holes are then coupled to electrons stored in the silicon nitride film 1032, thereby erasing the stored information of the Bit R. Since the number of electrons to be erased is small, its erase is completed in a short time in the range of about 1 to 10 xcexcs. By reversing the voltages applied to the impurity diffusion regions 10712 and 10723, erase related to the Bit L can be performed as shown in FIG. 64(B).
FIGS. 65(A) and 65(B) are schematic diagrams illustrating read operation. FIG. 65(A) shows the read operation from the Bit R. A voltage of VD=1.5 V is applied to the impurity diffusion region 10712 functioning as a drain region, a voltage of VS=0 V is applied to the impurity diffusion region 10723 functioning as a source region, and a voltage of VG=3 V is applied to the gate electrode 1091. By applying a voltage of VD=1.5 V to the impurity diffusion region 10712, channel current is allowed to flow to the impurity diffusion region 10712, irrespective of the contents stored in the Bit L. When electrons are stored in the silicon nitride film 1032 of the Bit R, it is in a state raised in threshold voltage, and no channel current flows even by applying a voltage of 3V to the gate electrode 1091. On the other hand, when no electrons are stored in the silicon nitride film 1032 of the Bit R, it is in a state lowered in threshold voltage, and channel current flows by applying a voltage of 3V to the gate electrode 1091. Therefore, the stored information of the Bit R can be read by detecting drain current or drain voltage. By reversing the voltages applied to the impurity diffusion regions 10712 and 10723, the read from the Bit L can be performed as shown in FIG. 65(B).
FIG. 66 is a circuit diagram illustrating a memory cell array configuration in a conventional NROM type non-volatile semiconductor memory. Bit lines form a hierarchical structure of main bit lines MBL1 and MBL2 and sub-bit lines SBL1 to SBL5. The bit lines BL1 and BL2 shown in FIG. 61 and the impurity diffusion regions 10712 and 10723 shown in FIG. 62 correspond to the sub-bit lines SBL1 to SBL5 in FIG. 66. Although two main bit lines MBL1 and MBL2 and five sub-bit lines SBL1 to SBL5 are depicted in FIG. 66, these numbers are cited merely by way of example and without limitation. The sub-bit lines SBL2 to SBL4, except for the sub-bit lines SBL1 and SBL5 at the opposite ends, are common to two memory cells adjacent each other in the row direction, thereby realizing a high integration degree of the memory cell array.
Selective transistors ST1a to ST4a and ST2b to ST5b are respectively connected to the opposite ends of the sub-bit lines SBL1 to SBL5. The selective transistors ST1a to ST4a are connected to the main bit line MBL1, and the selective transistors ST2b to ST5b are connected to the main bit line MBL2. The gates of the selective transistors ST1a to ST4a and ST2b to ST5b are connected to selective wirings SL1a to SL4a and SL2b to SL5b, respectively. Connection between the main bit lines MBL1, MBL2, and the sub-bit lines SBL1 to SBL5, can be controlled by a voltage applied to the selective wirings SL1a to SL4a and SL2b to SL5b. 
Taking the memory cell transistor MT11 as example, consider the case of performing the wire operation shown in FIG. 63(A). Firstly, a voltage of 0 V is applied to the main bit line MBL1, and a voltage of 4 V is applied to the main bit line MBL2. Then, a voltage of 1.5 V+Vth is applied to the selective wiring SL1a, and a voltage of 4 V+Vth is applied to the selective wiring SL2b. As used herein, xe2x80x9cVthxe2x80x9d is a threshold voltage of the selective transistors ST1a to ST4a and ST2b to ST5b. Accordingly, a voltage of 0 V and a voltage of 4 V are applied to the sub-bit lines SBL1 and SBL2, respectively. Subsequently, by applying a voltage of 8 V to the word line WL1, electrons are introduced into the ONO film on the sub-bit line SBL2 side of the memory cell transistor MT11, thereby performing write to the Bit R.
FIG. 67 is a timing chart illustrating each of write, read and erase operations related to the Bit R of the memory cell transistor MT11. The write operation is as described above. When performing read operation, a voltage of 1.5 V and a voltage of 0 V are applied to the main bit lines MBL1 and MBL2, respectively, a voltage of 1.5 V+Vth is applied to the selective wirings SL1a and SL2b, and a voltage of 3 V is applied to the word line WL1. In performing erase operation, a voltage of 0V and a voltage of 4 V are applied to the main bit lines MBL1 and MBL2, respectively, a voltage of 1.5 V+Vth and a voltage of 4 V+Vth are applied to the selective wirings SL1a and SL2b, respectively, and a voltage of xe2x88x926 V is applied to the word line WL1. When using two power sources of 1.5 V and 0 V, other voltages of 8V, 4 V, 3 V and xe2x88x926 V are required to generate in the interior of a chip.
However, the foregoing conventional non-volatile semiconductor memory has suffered from the following problems.
FIG. 68 is a sectional view illustrating the structure of two memory cell transistors MT12 and MT13 adjacent each other in the row direction. An impurity diffusion region 10723 is common to the two memory cell transistors MT12 and MT13. Part of the conductive film 1091 which is located on an ONO film 1052 functions as the gate electrode of the memory cell transistor MT12, and part of the conductive film 1091 which is located on an ONO film 1053 functions as the gate electrode of the memory cell transistor MT13. The gate electrode of the memory cell transistor MT12 and the gate electrode of the memory cell transistor MT13 are electrically connected via part of the conductive film 1091 which is located on an isolation insulating film 10623.
It is assumed that in the Bit R of the memory cell transistor MT12 and the Bit L of the memory cell transistor MT13, electrons are stored in both of the ONO films 1052 and 1053. Consider now the case of erasing the contents stored in the Bit R of the memory cell transistor MT12. In this case, by applying a voltage of 0 V to the impurity diffusion region 10712, a voltage of 4 V to the impurity diffusion region 10723, and a voltage of xe2x88x926 V to the conductive film 1091, hot holes are introduced into the ONO film 1052, thereby erasing the stored contents.
At this time, due to the application of the voltage of 4 V to the impurity diffusion region 10723, hot holes are also induced in the adjacent memory cell transistor MT13 that is not selected. Further, since the voltage of xe2x88x926 V is applied to the gate electrode of the memory cell transistor MT13, the inducted hot holes are introduced into the ONO film 1053. As a result, the contents stored in the Bit L of the non-selected memory cell transistor MT13 is erased. Thus, with the conventional non-volatile semiconductor memory, when easing the stored contents of the memory cell transistor, the stored contents of the adjacent non-selected memory cell transistor are also erased. That is, there has been the problems of causing disturb failure during erasing.
Referring to FIG. 62, in the NROM type memory cell transistor, the n+ type impurity diffusion region 107 is formed in the silicon substrate 101, and the impurity diffusion region 107 corresponds to the sub-bit line SBL in FIG. 66. For instance, the sheet resistance of the word line WL of polycide structure is about 5 to 6 xcexa9/xe2x96xa1, whereas the sheet resistance of the n+ type impurity diffusion region 107 is about 100 xcexa9/xe2x96xa1. Accordingly, a delay time of signal transmission in the sub-bit line SBL is larger than that in the word line WL. This results in the problem that the operation speed of the memory cell transistors is lowered as a whole.
As set forth, in the NROM type memory cell transistor, the contents stored in a memory cell transistor is read by detecting as to whether the transistor has a high or low threshold voltage resulting from the presence or absence of electrons stored in the ONO film 105. In order to accurately read the stored contents of the memory cell transistor, it is desirable that there is a large difference between a threshold voltage when electrons are stored in the ONO film 105 and a threshold voltage when no electrons are stored therein, namely that the threshold voltage distribution is sharp.
FIG. 69 is a diagram showing a threshold voltage distribution. The threshold voltage distribution of the memory cell transistor when electrons are stored in the ONO film 105 corresponds to xe2x80x9c0xe2x80x9d, and that when no electrons are stored therein corresponds to xe2x80x9c1xe2x80x9d. A larger difference between the maximum value of the distribution xe2x80x9c0xe2x80x9d and the minimum value of the distribution xe2x80x9c1xe2x80x9d (hereinafter referred to as xe2x80x9cWINDOWxe2x80x9d) permits more accurate read of the stored contents of the memory cell transistor. However, as shown in FIG. 69, the WINDOW that is relatively large in the initial state is gradually smaller as the operation of the memory cell transistor is repeated.
FIG. 70 is a sectional view illustrating a conventional memory cell transistor structure. Referring to FIG. 70, the miniaturization of WINDOW is caused by the fact that electrons trapped and stored by the traps at the end portions of the silicon nitride film 103 gradually move to the center by means of hopping or the like. Such a conventional non-volatile semiconductor memory suffers from the problem that as the operation of a memory cell transistor is repeated, the WINDOW is gradually smaller, thus failing to accurately read the stored contents of the memory cell transistor.
According to a first aspect of the invention, a non-volatile semiconductor memory comprises: a semiconductor substrate; plural memory cell transistors disposed in the form of a matrix in the semiconductor substrate; plural bit lines disposed at each column of the matrix; and plural word lines disposed at each row of the matrix, wherein the word lines have plural sub-word lines; and gate electrodes of the memory cell transistors adjacent each other in the row direction of the matrix are connected to the sub-word lines different from each other.
According to a second aspect of the invention, the non-volatile semiconductor memory of the first aspect further comprises an interlayer insulating film covering the memory cell transistors, and is characterized in that the sub-word lines extend in the row direction of the matrix and are disposed in the interlayer insulating film; that the gate electrodes are disposed on the semiconductor substrate via a gate insulting film capable of storing electrons, and are connected to the sub-word lines via a plug disposed in the interlayer insulating film; and that a wide portion of the gate electrodes is disposed at a contact portion between the gate electrodes and the plug.
According to a third aspect of the invention, the non-volatile semiconductor memory of the first aspect further comprises an interlayer insulating film covering the memory cell transistors, and is characterized in that the sub-word lines extend in the row direction of the matrix and are disposed in the interlayer insulating film; that the gate electrodes are disposed on the semiconductor substrate via a gate insulting film capable of storing electrons, and are connected to the sub-word lines via a plug disposed in the interlayer insulating film; and that the plug is in contact with the central portion of the gate electrodes.
According to a fourth aspect of the invention, the non-volatile semiconductor memory of the first aspect further comprises an interlayer insulating film covering the memory cell transistors, and is characterized in that the sub-word lines are disposed in the interlayer insulating film; that the gate electrodes are disposed on the semiconductor substrate via a gate insulting film capable of storing electrons, and are connected to the sub-word lines via a plug disposed in the interlayer insulating film; and that the sub-word lines extend linearly in the row direction of the matrix.
According to a fifth aspect of the invention, the non-volatile semiconductor memory of the first aspect is characterized in that the bit lines have an impurity diffusion region extending in the column direction of the matrix and being disposed in the semiconductor substrate, further comprises: an interlayer insulating film covering the memory cell transistors; and wiring extending in the column direction of the matrix and being disposed in the interlayer insulating film, the wiring being connected to the impurity diffusion region via a plug disposed in the interlayer insulating film and having higher conductivity than the impurity diffusion region.
According to a sixth aspect of the invention, the non-volatile semiconductor memory of the first aspect is characterized in that the sub-word lines extend in the row direction of the matrix and have a portion functioning as the gate electrodes of the memory cell transistors and overlying the semiconductor substrate via a gate insulating film capable of storing electrons, further comprises: an interlayer insulating film covering the memory cell transistors; and wiring extending in the row direction of the matrix and being disposed in the interlayer insulating film, the wiring being connected to the sub-word lines via a plug disposed in the interlayer insulating film and having higher conductivity than the sub-word lines.
According to a seventh aspect of the invention, the non-volatile semiconductor memory of one of the first to sixth aspects is characterized in that the gate electrodes are disposed on a main surface of the semiconductor substrate via a gate insulating film having a charge storing region capable of storing charge; that the memory cell transistors further have source/drain regions disposed in the main surface of the semiconductor substrate; and that the charge storing region is disposed only in the end portion of the gate insulating film adjacent to the source/drain regions.
According to an eighth aspect of the invention, the non-volatile semiconductor memory of the seventh aspect is characterized in that the gate insulating film is a silicon oxide film; and that the charge storing region is a polysilicon film disposed in the silicon oxide film.
According to a ninth aspect of the invention, the non-volatile semiconductor memory of one of the first to eighth aspects further comprises: a detecting circuit to detect a bit line to be activated from the plural bit lines, based on a column address signal; and a selecting circuit to select a sub-word line to be activated from the plural sub-word lines, based on a row address signal and the result of detection of the detecting circuit.
According to a tenth aspect of the invention, the non-volatile semiconductor memory of one of the first to eighth aspects is characterized in that the word lines have two sub-word lines, further comprises: a parity check circuit to detect the parity of a column address signal; and a selecting circuit to select one sub-word line to be activated from the two sub-word lines, based on a row address signal and the result of detection of the parity check circuit.
According to an eleventh aspect of the invention, the non-volatile semiconductor memory of the first aspect further comprises a first isolation insulating film of trench type being disposed in a main surface of the semiconductor substrate and isolating the memory cell transistors adjacent each other in the row direction of the matrix, and is characterized in that the bit lines have an impurity diffusion region disposed in the interface between the semiconductor substrate and the first isolation insulating film.
According to a twelfth aspect of the invention, the non-volatile semiconductor memory of the eleventh aspect is characterized in that the semiconductor substrate has a memory cell array part in which the plural memory cell transistors are disposed, and a peripheral circuit part in which a peripheral circuit for controlling the memory cell transistors is disposed, further comprises a second isolation insulating film of trench type disposed at the boundary portion between the memory cell array part and the peripheral circuit part in the main surface of the semiconductor substrate, the second isolation insulating film being deeper than the first isolation insulating film.
According to a thirteenth aspect of the invention, the non-volatile semiconductor memory of the eleventh or twelfth aspect is characterized in that the gate electrodes are formed so as to overlie the end portion of the first isolation insulating film at the boundary portion with the main surface of the semiconductor substrate; and that a recess buried with the gate electrodes is disposed in the upper surface of the end portion of the first isolation insulating film.
According to a fourteenth aspect of the invention, the non-volatile semiconductor memory of one of the eleventh to thirteenth aspects is characterized in that the first isolation insulating film has a cross-section of substantially T-shape of which central portion has a larger depth than its end portion; and that the impurity diffusion region of one of the memory cell transistors and the impurity diffusion region of the other memory cell transistor adjacent to the one memory cell transistor via the first isolation insulating film, are isolated by the central portion of the first isolation insulating film.
According to a fifteenth aspect of the invention, the non-volatile semiconductor memory of one of the first to fourteenth aspects is characterized in that the semiconductor substrate is a semiconductor layer of an SOI substrate having such a structure that a support substrate, an insulating layer and the semiconductor layer are stacked in this order.
According to a sixteenth aspect of the invention, the non-volatile semiconductor memory of the twelfth aspect is characterized in that the semiconductor substrate is a semiconductor layer of an SOI substrate having such a structure that a support substrate, an insulating layer and the semiconductor layer are stacked in this order; and that the second isolation insulating film is in contact with the insulating layer.
According to a seventeenth aspect of the invention, the non-volatile semiconductor memory of the twelfth aspect is characterized in that the semiconductor substrate is a semiconductor layer of an SOI substrate having such a structure that a support substrate, an insulating layer and the semiconductor layer are stacked in this order; and that the bottom surface of the second isolation insulating film is present in the semiconductor layer.
According to an eighteenth aspect of the invention, a non-volatile semiconductor memory comprises: a semiconductor substrate; plural memory cell transistors disposed in the form of a matrix in the semiconductor substrate; plural bit lines disposed at each column of the matrix; plural word lines disposed at each row of the matrix; and an interlayer insulating film covering the memory cell transistors, wherein the bit lines have an impurity diffusion region extending in the column direction of the matrix and being disposed in the semiconductor substrate, further comprises wiring extending in the column direction of the matrix and being disposed in the interlayer insulating film, the wiring being connected to the impurity diffusion region via a plug disposed in the interlayer insulating film and having higher conductivity than the impurity diffusion region.
According to a nineteenth aspect of the invention, the non-volatile of semiconductor memory of the eighteenth aspect is characterized in that the word lines extend in the row direction of the matrix and have a portion functioning as the gate electrodes of the memory cell transistors and overlying the semiconductor substrate via a gate insulating film capable of storing electrons; further comprises: wiring extending in the row direction of the matrix and being disposed in the interlayer insulating film, the wiring being connected to the word lines via a plug disposed in the interlayer insulating film and having higher conductivity than the word lines.
According to a twentieth aspect of the invention, a non-volatile semiconductor memory comprises: a semiconductor substrate; and plural memory cell transistors disposed in the form of a matrix in the semiconductor substrate, the memory cell transistors having a gate insulating film being disposed on a main surface of the semiconductor substrate and having a charge storing region capable of storing charge; a gate electrode disposed on the gate insulating film; and source/drain regions disposed in the main surface of the semiconductor substrate, the charge storing region being disposed only in the end portion of the gate insulating film adjacent to the source/drain regions.
In the first aspect, different voltages can be applied individually to each gate electrode of the memory cell transistors adjacent each other in the row direction of the matrix. This enables avoiding the occurrence of disturb failure during erasing.
In the second aspect, there is the effect of increasing mask alignment offset margin when alignment with the gate electrodes is made to form the plug in the interlayer insulating film.
In the third aspect, there is also the effect of increasing mask alignment offset margin when alignment with the gate electrodes is made to form the plug in the interlayer insulating film.
In the fourth aspect, as compared to the case that the sub-word lines snake and extend in the row direction, the wiring length of the sub-word lines is shortened thereby to reduce a delay time of signal transmission in the sub-word lines.
In the fifth aspect, by arranging such that the wiring of low resistance is connected via the plug to the impurity diffusion region, the resistance value of the bit lines can be lowered thereby to reduce the delay time of signal transmission in the bit lines.
In the sixth aspect, by connecting the wiring of low resistance to the sub-word lines, the resistance value of the sub-word lines can be lowered thereby to reduce the delay time of signal transmission in the sub-word lines.
In the seventh aspect, it is able to suppress the charge stored in the charge-storing region from diffusing in the gate insulating film. This enable to suppress the miniaturization of WINDOW caused by the repetitive operation of the memory cell transistors.
In the eighth aspect, charge can be stored in the polysilicon film functioning as a floating gate. Further, since the gate insulating film is composed of a silicon oxide film having less traps, the miniaturization of WINDOW can be effectively suppressed.
In the ninth aspect, the selecting circuit can select a suitable sub-word line from a plurality of sub-word lines that belong to the same row in the matrix, depending on the bit line to be activated.
In the tenth aspect, the selecting circuit can select a suitable sub-word line from two sub-word lines that belong to the same row in the matrix, depending on the parity of a row address signal.
In the eleventh aspect, as compared to the case of having the LOCOS type isolation insulating film, the area occupied by a bird""s beak is reduced to increase the integration degree of the chip.
The twelfth aspect enables to suppress the interference between the memory cell transistors and the peripheral circuit.
In the thirteenth aspect, the efficiency of write and erase operations can be increased because the field strength is increased at the portion having the recess.
In the fourteenth aspect, the occurrence of disturb failure during erasing can be avoided because the impurity diffusion region of one memory cell transistor and the impurity diffusion region of the other memory cell transistor are separated by the central portion of the first isolation insulating film.
In the fifteenth aspect, resistance to soft error can be improved and, by reducing parasitic capacity, the operation speed can be increased.
In the sixteenth aspect, the semiconductor layer in the memory cell array part and the semiconductor layer in the peripheral circuit part are electrically isolated by the second isolation insulating film, thereby completely preventing the interference between the memory cell transistors and the peripheral circuit.
In the seventeenth aspect, the semiconductor layer in the memory cell array part and the semiconductor layer in the peripheral circuit part are electrically connected with each other. Therefore, when fixing the body potential of the memory cell transistors and the transistors of the peripheral circuit part, the body voltage generating circuit can be shared between the memory cell array part and the peripheral circuit part.
In the eighteenth aspect, by arranging such that the wiring of low resistance is connected via the plug to the impurity diffusion region, the resistance value of the bit lines can be lowered thereby to reduce the delay time of signal transmission in the bit lines.
In the nineteenth aspect, by connecting the wiring of low resistance to the word lines, the resistance value of the word lines can be lowered thereby to reduce the delay time of signal transmission in the word lines.
In the twentieth aspect, it is able to suppress the charge stored in the charge storing region from diffusing in the gate insulating film, thereby to suppresses the miniaturization of WINDOW caused by the repetitive operation of the memory cell transistors.
It is an object of the present invention to overcome the foregoing problems by providing a non-volatile semiconductor memory that can suppress or avoid disturb failure during erase operation, can suppress a reduction in operation speed of memory cell transistors due to high resistance of sub-bit lines, and can avoid malfunction of the memory cell transistors due to the miniaturization of WINDOW.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.